When Ldaxr Doesn't Work: Exclusive Accesses and Cacheability on AArch64

The author describes implementing a spin lock for their AArch64 operating system kernel and discovering a critical difference between QEMU simulation and real hardware: the load exclusive (ldaxr) instruction raises an exception on real Raspberry Pi hardware but not in QEMU. The post explores how memory cacheability, virtual memory configuration, and memory attributes interact with exclusive memory operations to cause this discrepancy, highlighting how real hardware testing reveals failure modes that emulation can miss.