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A recent LLVM patch introduced ordered vector reductions to optimize floating-point addition chains, but it caused a significant performance regression by failing to account for the cost of storing scalar values to memory before performing the vector reduction. The new approach unnecessarily spills data to the stack and performs expensive memory loads, making it more costly than the original scalar chain of additions it was meant to replace. The issue was identified through benchmark analysis on a RISC-V target, showing an 89% performance delta with increased instruction counts and execution cycles.
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