The DRAM interface and the PHY (why a DDR3+ interface must be tuned at boot)

Modern DDR3+ DRAM interfaces require tuning at boot because data transfer occurs at rates where the controller's clock cannot reliably sample incoming data due to board and chip delays. Instead, DDR memories use differential data strobes (DQS) to sample data on both clock edges, with each of the eight-bit byte lanes routed separately and calibrated individually. The DRAM interface involves bidirectional data signals, command/address signals, and various control signals that must be precisely synchronized through leveling procedures, termination settings, and reference voltage configuration.