Programmable Probabilistic Computer with 1M p-bits

Researchers have developed a programmable probabilistic computer with one million p-bits by networking multiple FPGAs into a distributed Ising machine, achieving over a trillion p-bit flips per second while maintaining all coupling weights in local memory. The study identifies a critical design parameter—the ratio of boundary-exchange frequency to local update frequency—that determines when a distributed system performs equivalently to a single-chip system, establishing a quantifiable tradeoff between parallelism and accuracy. This architecture and theoretical framework provide scalable design rules for building probabilistic computers beyond single-chip limitations and demonstrate applications across spin glasses, optimization problems, and Boolean satisfiability.