I designed a nibble-oriented CPU in Verilog to build a scientific calculator

A developer created a fully functional scientific calculator implemented in hardware on an FPGA using a custom nibble-oriented (4-bit) soft CPU written in Verilog, along with microcode firmware and supporting tools. The project includes multiple build targets such as a Qt simulator, command-line test harness, and FPGA synthesis options, with comprehensive documentation and a web browser demo available. The work is open-source under a Creative Commons Attribution-NonCommercial-ShareAlike license and includes research projects for algorithm verification and hardware testing.